1. Field of the Invention
The present invention relates to a logic circuit employed in a floating-point arithmetic unit, etc. so as to detect prediction error in a cancelling bit prediction circuit which is used in a mantissa normalization circuit, and a floating-point arithmetic unit having a function of detecting cancelling prediction error.
2. Description of the Related Art
In order to true up or justify leftward most significant bits of the mantissas onto a particular position or digit, normalization process is needed in the floating-point arithmetic unit after a calculating operation has been completed. This normalization process is such a process that the number of "0's" or "1's" which are aligned continuously from the most significant digits of the arithmetic result are counted and then the arithmetic result is shifted left by digits corresponding to the counted number of leading "0's" or leading "1's".
With the progress of the processor speed, such a method has been proposed that enables to predict the number of "0's" or "1's" which are aligned continuously from the most significant digits of the arithmetic result in parallel with the calculation process (cancelling prediction system or cancelling prediction circuit). According to this method, an amount of the left shift to be executed in the normalization process can be predicted based on the operand. Such cancelling prediction system has been set forth in papers published by E. HOKENEK (IBM, J. RES. DEVELP. VOL. 34, 1990, pp. 71-77), H. SUZUKI et al. (CICC proc., 1995, pp.27.5.1-27.5.4), etc.
FIG. 1 is a state transition diagram explaining a basic principle of the above cancelling prediction (leading zero/one anticipation).
First, two numbers A, Bx are compared with each other bit by bit and then, according to respective compared states, a signal G (both are "1's"), a signal Z (both are "0's"), and a signal P (they are "1" and "0") which represent following three states respectively are defined. Where "and" denotes a logical product; "or", a logical sum; "xor", exclusive logical sum; and "not", negative logic.
g&lt;i&gt;=A&lt;i&gt; and Bx&lt;i&gt;, PA1 p&lt;i&gt;=A&lt;i&gt; xor Bx&lt;i&gt;, and PA1 z&lt;i&gt;=not (A&lt;i&gt; or Bx&lt;i&gt;). PA1 g&lt;i&gt;=A&lt;i&gt; and Bx&lt;i&gt; PA1 p&lt;i&gt;=A&lt;i&gt; xor Bx&lt;i&gt; PA1 z&lt;i&gt;=not (A&lt;i&gt; or Bx&lt;i&gt;) PA1 g&lt;n&gt;=SA and SB PA1 p&lt;n+1&gt;=p&lt;n&gt;=SA xor SB PA1 z&lt;n&gt;=not (SA or SB), PA1 EZ&lt;i&gt;=((not p&lt;i+2&gt;) and (((g&lt;i+1&gt; and (not g&lt;i&gt;)) or (z&lt;i+1&gt; and (not z&lt;i&gt;)))) or ((p&lt;i+2&gt;) and (((g&lt;i+1&gt; and (not z&lt;i&gt;)) or (z&lt;i+1&gt; and (not g&lt;i&gt;)))). PA1 C&lt;k&gt;=g&lt;k&gt; or (p&lt;k&gt; and g&lt;k-1&gt;) or (p&lt;k&gt; and p&lt;k-1&gt; and g&lt;k-2&gt;) or (p&lt;k&gt; and p&lt;k-1&gt; and p&lt;k-2&gt; and g&lt;k-3&gt; or . . . or (p&lt;k&gt; and p&lt;k-1&gt; and p&lt;k-2&gt; and . . . and p&lt;2&gt; and p&lt;1&gt; and g&lt;0&gt;) or (p&lt;k&gt; and p&lt;k-1&gt; and p&lt;k-2&gt; and . . . and p&lt;2&gt; and p&lt;1&gt; and p&lt;0&gt; and Cin), PA1 the prediction error detecting signal at a k-th bit is set to C&lt;k&gt; in case Cin=1 when the high/low comparator has decided that a result of subtraction A-B is positive, and the prediction error detecting signal at the k-th bit is set to (not C&lt;k&gt;) in case Cin=1 when the high/low comparator has decided that the result of subtraction A-B is negative.
Any of three these signals becomes "1" from the most significant bit. Therefore, if the states are checked based on the signal from the most significant bit to the least significant bit in compliance with the state transition diagram having three states shown in FIG. 1, the bit at which cancelling occurs can be specified.
According to the paper published by H. SUZUKI et al., only the prediction signals (cancelling prediction signals) which are so predicted that cancelling can be generated from the Z-state shown in FIG. 1 can be extracted, and then the most significant bit signals can be detected from such prediction signals by priority encoders. With the use of the fact that high/low relationship between two numbers has already been known, a logic for generating the cancelling prediction signals can be simply implemented by this cancelling prediction circuit. In other words, in the case of subtraction, since order of two numbers is switched according to the high/low relationship between two numbers so as to assure that the remainder becomes surely positive, there exist no transition to the G-state.
FIG. 2 is a block diagram showing a configuration of a floating-point arithmetic unit in the prior art. FIG. 3 is a conceptional view showing the lapse of time in an operation of the floating-point arithmetic unit shown in FIG. 2.
The floating-point arithmetic unit comprises a high/low comparator 1100 for comparing high/low of two operands A&lt;31:0&gt; and B&lt;31:0&gt;; a pair of selectors 1103 and a pair of inverters 1104 for inverting either of two operands A&lt;31:0&gt; and B&lt;31:0&gt; based on the result of the high/low comparison in the case of subtraction; an arithmetic unit (adder) 1101 for receiving respective outputs of the pair of selectors 1103; and a Leading zero/one anticipator (cancelling prediction circuit) 1102 for executing the above cancelling prediction.
Although an explanation is made herein under the assumption that the operand B&lt;31:0&gt; is smaller than the operand A&lt;31:0&gt;, generality is not lost. Inverted bit data of the operand B&lt;31:0&gt; is expressed as Bx&lt;31:0&gt;. A cancelling prediction operation executed by the cancelling prediction circuit 1102 (period T1 in FIG. 3) can be carried out in parallel with an add-subtract operation executed by the arithmetic unit 1101 (period T2 in FIG. 3).
A left shifter 1105 is connected to the output side of the arithmetic unit 1101. With the use of a shift amount control signal S100 which is the result of the Leading zero/one Anticipator (cancelling prediction circuit) 1102 for executing the above cancelling prediction, the left shifter 1105 can execute a left shift operation (period T3 in FIG. 3) in order to execute the above normalization process. In addition, a rounding processor 1106 can execute rounding process to round up the arithmetic result of the arithmetic unit 1101 within the designated number of digit. Then, a selector 1107 can select one of the result of the rounding processor 1106 and the result of the left shifter 1105.
The left shifter 1105 used to execute the above normalization process can execute the left shift process by use of the result of the above Leading zero/one Anticipator (cancelling prediction circuit) 1102. However, since one bit prediction error is included in the shift amount control signal S100 which is the result of the Leading zero/one Anticipator (cancelling prediction circuit) 1102, one bit error correction shift (right shift) is executed by a right shifter 1108 in the wake of the left shift operation to carry out the normalization process.
One bit prediction error can be detected (period T4 in FIG. 3) by examining the most significant bit (MSB) of the output of the left shifter 1105 (i.e., normalized arithmetic result). According to this result, the right shifter 1108 can determine whether or not one bit error correction shift must be executed (period T5 in FIG. 3). At this time, the most significant bit of the result of the left shifter 1105 can be supplied to the right shifter 1108 via a buffer 1109.
However, in the floating-point arithmetic unit in the prior art, following problems have arisen.
As described above, one bit error correction shift must be effected after the normalization process (left shift operation) since one bit prediction error is included in the result of the cancelling prediction circuit 1102. At this time, it has been decided by examining the most significant bit of the arithmetic result whether or not one bit error correction shift must be executed.
In the event that the one bit error correction shift is needed or not by checking the most significant bit of the normalized arithmetic result, there has been a possibility that, if a delay time in the buffer 1109 to drive the right shifter 1108 is taken into consideration, this one bit prediction error detection becomes a critical path.
In addition, in the event that the cancelling prediction bit signal is prepared with the use of the fact that the high/low relationship between two numbers has already been known, such high/low relationship between two numbers must be decided before execution of the calculation. As a result, a delay time in the high/low comparator has been added to this computing time.